This invention relates generally to semiconductor electrically erasable programmable read only memories (EEprom), and specifically to circuits and techniques for reading and programming their state.
EEprom and electrically programmable read only memory (Eprom) are typically used in digital circuits for non-volatile storage of data or program. They can be erased and have new data written or "programmed" into their memory cells.
An Eprom utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned "on" to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate.
The floating gate can hold a range of charge and therefore an Eprom memory cell can be programmed to any threshold level within a threshold window. The size of the threshold window, delimited by the minimum and maximum threshold levels of the device, depends on the device's characteristics, operating conditions and history. Each distinct threshold level within the window may, in principle, be used to designate a definite memory state of the cell.
For Eprom memory, the transistor serving as a memory cell is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory states are erasable by removing the charge on the floating gate by ultra-violet radiation.
An electrically erasable and programmable read only memory (EEprom) has a similar structure but additionally provides a mechanism for removing charge from its floating gate upon application of proper voltages. An array of such EEprom cells is referred to as a "Flash" EEprom array when an entire array of cells, or significant group of cells of the array, is erased simultaneously (i.e., in a flash). Once erased, a cell can then be reprogrammed.
A specific, single cell in a two-dimensional array of Eprom, EEprom cells is addressed for reading by application of a source-drain voltage to source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to a word line connected to the control gates in a row containing the cell being addressed.
An addressed memory cell transistor's state is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain. The level of current is proportional to the threshold level of the transistor, which in turn is determined by the amount of charge on its floating gate.
In the usual two-state EEprom cell, one breakpoint threshold level is established so as to partition the threshold window into two regions. The source/drain current is compared with the breakpoint threshold level that was used when the cell was programmed. If the current read is higher than that of the threshold, the cell is determined to be in a "zero" state, while if the current is less than that of the threshold, the cell is determined to be in the other state. Thus, such a two-state cell stores one bit of digital information. A current source which may be externally programmable is often provided as part of a memory system to generate the breakpoint threshold current.
Thus, for a multi-state EEprom memory cell, each cell stores two or more bits of data. The information that a given EEprom array can store is thus increased by the multiple of number of states that each cell can store.
Accordingly, it is a primary object of the present invention to provide a system of EEprom memory cells wherein the cells are utilized to store more than one bit of data.
It is a further object of the present invention to provide improved read circuits as part of an Eprom or EEprom integrated circuit memory chip.
It is also an object of the invention to provide read circuits which are simpler, easier to manufacture and have improved accuracy and reliability over an extended period of use.
It is also an object of the present invention to provide improved program circuits as part of an Eprom or EEprom integrated circuit memory chip.
It is also an object of the invention to provide program circuits which are simpler, easier to manufacture and have improved accuracy and reliability over an extended period of use.
It is another object of the present invention to provide memory read and program techniques that automatically compensate for effects of temperature, voltage and process variations, and charge retention.
It is yet another object of the present invention to provide Flash EEprom semiconductor chips that can replace magnetic disk storage devices in computer systems.
Further, it is an object of the present invention to provide a Flash EEprom structure capable of an increased lifetime as measured by the number of program/read cycles that the memory can endure.